The invention relates to semiconductor circuit devices, and more particularly to charge pump circuits for providing a voltage to various components on semiconductor integrated circuits. The invention is particularly applicable to dynamic random access memory device (DRAMS).
In order to pass a full charge to a DRAM memory cell through an n-channel access transistor, it is necessary to drive the gate of the n-channel access transistor to a voltage greater than the voltage used to charge the storage capacitor. Modem dynamic random access memories (DRAMs) use charge pumps to generate this higher potential. U.S. Pat. No. 5,038,325, entitled xe2x80x9cHigh Efficiency Charge Pump Circuitxe2x80x9d describes one charge pump and is herein incorporated by reference.
In order to pass a full charge to a DRAM memory cell through an n-channel access transistor, it is necessary to drive the gate of the n-channel access transistor to a voltage greater than the voltage used to charge the storage capacitor. Modem dynamic random access memories (DRAMs) use charge pumps to generate this higher potential.
A typical external supply potential is referred to as VCCX. VCCX is often regulated. The internally regulated potential is referred to as VCC. In many applications VCCX is equal to 5 volts and VCC is regulated to 3.3 volts. A potential generated in a charge pump is generally referred to as VCCP. In typical cases VCCP is two volts greater than the DRAM""s internal regulated voltage, or two volts above VCCX for DRAM""s that do not use a regulated VCC.
Previous charge pump circuits have had difficulty operating with a VCC below three volts. There have been attempts to design circuits to overcome this problem.
In one attempt to increase the efficiency of a charge pump having a regulated supply potential, a level translator circuit was added between the logic of the pump, and the pump capacitors. The level translator allowed the circuit to draw current from the external power source VCCX rather than the regulated source VCC. With this circuit a potential of (2VCCXxe2x88x92Vt) could be passed through a pump n-channel transistor as VCCP, where Vt is the threshold voltage of the pump n-channel transistor. Thus for a VCCX of 4 volts, the VCCP is equal to 7 volts for a Vt of 1 volt. This is sufficient for transferring a full VCC into a memory location of a DRAM. In early regulated devices, VCC may range from 3.5 to 4 volts. However, there is currently a trend toward lower levels of VCCX. Current specifications require VCCX of 2.7 to 3.6 volts, and the trend is toward even lower VCCX levels. In systems with low VCCX, there is no longer a need for a regulated VCC. Instead VCCX is used throughout the circuit. VCCP is still required to pass a full VCCX in to the DRAM memory cell. As VCCX is reduced, the efficiency of the VCCP pump is also reduced since the charge available for transfer to VCCP is proportional to VCCX times the capacitance of the pump capacitor. Thus as VCCX values are reduced conventional pump mechanisms eventually fail to function.
In another attempt 2VCCX can be passed through as VCCP in a two stage pump by using one pump to generate the entire supply voltage for a second pump. This approach is inefficient for a low level supply potential and is impractical since all the charge eventually is generated from the first pump. In this configuration a very large first stage pump is required to provide the required supply potential for the second stage pump.
Thus a need exist to provide a pumped potential at the gate of the access transistor such that the full charge on the memory storage capacitor is passed through the access transistor for devices with low VCCX.
The invention includes a charge pump circuit for generating a pumped potential and methods of its operation. In one exemplary embodiment the pumped potential is used to pass a full charge to or from a storage capacitor of a dynamic random access memory (DRAM). An exemplary embodiment of a charge pump circuit in accordance with the present invention features a first stage circuit and a second stage circuit providing minimal loading of the first stage circuit by the second stage circuit. The pumped potential passed from the second stage circuit to a charge pump output node comes primarily from VCCX and not from the first stage pump. This allows the first stage to remain small.
In this exemplary embodiment the first stage circuit of the invention generates an intermediate pumped potential greater than an input supply potential. The intermediate pumped potential becomes a supply potential for a portion of the second stage circuit. The second stage circuit generates a pumped output potential greater than the intermediate pumped potential.
Both the first and second stage circuits have at least two capacitors, a small pump capacitor and a large pump capacitor. The first stage circuit of the above described exemplary embodinent supplies the increased intermediate pumped potential to those nodes which are used to charge the small pump capacitor of the second stage circuit. The input supply potential supplies the potential to those nodes which are used to charge the large pump capacitors of both stages and the small pump capacitor of the first stage circuit. The small pump capacitor of the second stage circuit, in turn, supplies the gate voltage to an n-channel pass transistor of the second stage circuit which passes a full charge from the large pump capacitor of the second stage circuit to the output. Charging only the small pump capacitor of the second stage circuit with the intermediate pumped potential minimizes the loading effect of the second stage circuit on the first stage circuit.
The first stage circuit is used to boost the efficiency of the second stage circuit. The loading on the first stage circuit is very small in comparison to the load which will be driven by the pumped output potential. Since the second stage circuit is operating off of the intermediate pumped potential generated from the first stage circuit, it is more efficient and is able to source the VCCP at a lower VCC or VCCX level than if the first and the second stage circuits were running in parallel.
In one embodiment a precharge circuit precharges a first terminal of the pass transistor to a potential equal to the intermediate potential minus a threshold voltage of the precharge circuit. A circuit comprising a level translator is responsive to the intermediate potential to generate a control potential at the gate of the pass transistor which is substantially equal to the boosted potential plus a threshold voltage of the precharge circuit.
Charge transfers from the first terminal to a second terminal of the pass transistor. The charge transferred is proportional to the capacitance of a capacitor charged to the boosted potential and the difference in potential between the boosted potential and the final output potential as long as the boosted potential is not limited by a pass device.
In a further embodiment the invention is a method which conserves power by adjusting the boosted potential and the control potential to have a difference substantially equal to a threshold voltage when the boosted potential is not limited by a pass device. The boosted potential is applied to the first terminal of the pass transistor and the control potential is applied to the gate of the pass transistor. The method comprises increasing an input supply potential to obtain an intermediate potential greater than the input supply potential, and precharging the first terminal or the pass transistor to equal the intermediate potential minus a threshold voltage of a circuit performing said step of precharging. The pass transistor is actuated and a potential substantially equal to the boosted potential is driven to a second terminal of the pass transistor.
In a further exemplary embodiment in accordance with the present invention there is included a voltage pump circuit and method using a periodic input signal to feed the precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of the pass transistor. When actuated the pass transistor drives the boosted potential lo an output node of the voltage pump circuit. The level translator circuit is supplied by the high potential of the periodic intermediate potential for the period of time surrounding the time the pass transistor is turned on.
In a further embodinent in accordance with the present invention, the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. In other words the activation of the pull down portion does not occur until the pull up portion has been deactivated due to the delay element delaying a gate control signal to a transistor of the pull down portion. Since the circuit and method of the invention substantially prohibit the simultaneous activation of the pull up and pull down portions of the level translator circuit crossing current and power consumption are reduced.
The invention also includes the method of maintaining deactivation of the pull down portion until the pull up portion has been activated. In one implementation, this is accomplished by delaying a control signal to the pull down portion.
In one embodiment in accordance with the further exemplary embodiment, the small capacitor is precharged by a precharge circuit of the invention which also responds to a periodic signal to precharge internal nodes of the voltage pump of the invention with a periodic signal.
In still a further embodiment in accordance with the further exemplary embodiment a first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other. A second diode clamp is connected between the terminals of the pass transistor so that the boosted potential does not need to climb above the output potential plus a Vt of second diode clamp. This in turn limits the gate potential of the transistor through the first diode clamp.